With integrated circuit frequencies reaching tens of GHz, new high-frequency phenomena are desirably modeled and analyzed during the circuit design process (e.g., during physical verification). As frequency increases, the representation of wires evolves from a single resistance in series with a capacitance to ground, to a distributed version of the same (a concatenation of RC segments or π sections), to an R, , C, distributed circuit. Furthermore, the conventional representations, valid for an isolated wire in the presence of a ground reference, are desirably expanded to include both the nature of the power and ground wires, with physical values for their respective inductance and resistance, as well as the mutual couplings among different wires.
To get an idea of the complexity associated with this problem, consider a typical circuit. A typical leading edge digital circuit at 65 nm contains approximately O(3*109) transistors, and approximately O(1010) wires. Each wire, on average, contains 10 segments, and the electrical properties of a wire are typically decomposed in terms of their constituent segments. Furthermore, each wire segment has on average a few segments that can be classified as nearest neighbors whose mutual couplings are desirably considered. The global storage demands for a description of this exemplary circuit amount to approximately: (1) 1011 real numbers for storing resistance values; (2) 1011 real numbers for storing capacitance to ground values; (3) 1022 real numbers for storing mutual capacitance values; (4) 10″ real numbers for storing self inductance values; and (5) 1022 complex numbers for storing mutual inductance values.
Because the computational and storage demands for this problem are undesirably large and impractical in real-world applications, computationally efficient, yet accurate, improved modeling and analysis techniques for parasitic effects in high-speed circuits are needed for circuit designers and for electronic design automation (EDA) software vendors that develop the tools used to create, simulate, verify, and optimize integrated circuit designs.